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PIC12CE5XX
8-Pin, 8-Bit CMOS Microcontroller with EEPROM Data Memory
Devices Included in this Data Sheet:
* PIC12CE518 * PIC12CE519
Pin Diagram:
PDIP, SOIC, Windowed CERDIP
VDD GP5/OSC1/CLKIN GP4/OSC2 GP3/MCLR/VPP 1 2 3 4 8 7 6 5 VSS GP0 GP1 GP2/T0CKI
High-Performance RISC CPU:
* Only 33 single word instructions to learn * All instructions are single cycle (1 s) except for program branches which are two-cycle * Operating speed: DC - 4 MHz clock input DC - 1 s instruction cycle Memory Device PIC12CE518 PIC12CE519 * * * * * EPROM Program 512 x 12 1024 x 12 RAM Data 25 x 8 41 x 8 EEPROM Data 16 x 8 16 x 8
PIC12CE518 PIC12CE519
Special Microcontroller Features:
* In-Circuit Serial Programming (ICSPTM) of program memory (via two pins) * Internal 4 MHz RC oscillator with programmable calibration * Power-on Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Wake-up from SLEEP on pin change * Internal weak pull-ups on I/O pins * Internal pull-up on MCLR pin * Selectable oscillator options: - INTRC: Internal 4 MHz RC oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - LP: Power saving, low frequency crystal
12-bit wide instructions 8-bit wide data path Special function hardware registers Two-level deep hardware stack Direct, indirect and relative addressing modes for data and instructions
Peripheral Features:
* 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler * 1,000,000 erase/write cycle EEPROM data memory * EEPROM data retention > 40 years
CMOS Technology:
* Low-power, high-speed CMOS EPROM/EEPROM technology * Fully static design * Wide temperature range: - Commercial: 0C to +70C - Industrial: -40C to +85C - Extended: -40C to +125C * Wide operating voltage range: -Commercial: 2.5V to 5.5V -Industrial: 2.5V to 5.5V -Extended: 2.5V to 5.5V * Low power consumption - < 2 mA typical @ 5V, 4 MHz - 15 A typical @ 3V, 32 kHz - < 1 A typical standby current
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 1
PIC12CE5XX
TABLE OF CONTENTS
1.0 General Description..................................................................................................................................................................... 3 2.0 PIC12CE5XX Device Varieties.................................................................................................................................................... 5 3.0 Architectural Overview ................................................................................................................................................................ 7 4.0 Memory Organization ................................................................................................................................................................ 11 5.0 I/O Port ...................................................................................................................................................................................... 19 6.0 EEPROM Peripheral Operation................................................................................................................................................. 21 7.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 27 8.0 Special Features of the CPU..................................................................................................................................................... 31 9.0 Instruction Set Summary ........................................................................................................................................................... 43 10.0 Development Support................................................................................................................................................................ 55 11.0 Electrical Characteristics - PIC12CE5XX .................................................................................................................................. 61 12.0 DC and AC Characteristics - PIC12CE5XX .............................................................................................................................. 77 13.0 Packaging Information............................................................................................................................................................... 81 Index .................................................................................................................................................................................................... 87 PIC12CE5XX Product Identification System........................................................................................................................................ 89
To Our Valued Customers
Most Current Data Sheet
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet. * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.
DS40172B-page 2
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
1.0 GENERAL DESCRIPTION
1.1 Applications
The 8-pin PIC12CE5XX from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/EEPROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/ single cycle instructions. All instructions are single cycle (1 s) except for program branches which take two cycles. The PIC12CE5XX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC12CE5XX products are equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC12CE5XX are available in the cost-effective One-Time-Programmable (OTP) versions which are suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP microcontrollers while benefiting from the OTP's flexibility. The PIC12CE5XX products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a `C' compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM(R) PC and compatible machines. The PIC12CE5XX series fits perfectly in applications ranging from sensory systems, gas detectors and security systems to low-power remote transmitters/ receivers. The EPROM programming technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. While the EEPROM data memory technology allows for the changing of calibrations factors and security codes, the small footprint 8-pin packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC12CE5XX series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of "glue" logic and PLD's in larger systems, coprocessor applications).
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 3
PIC12CE5XX
TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES
PIC12C508(A) PIC12C509(A) PIC12CE518 PIC12CE519 PIC12C671 Maximum Frequency of Operation (MHz) EPROM Program Memory RAM Data Memory (bytes) 4 4 4 4 10 PIC12C672 PIC12CE673 PIC12CE674 10 10 10
Clock
512 x 12
1024 x 12
512 x 12
1024 x 12
1024 x 14
2048 x 14
1024 x 14
2048 x 14
Memory
25
41
25
41
128
128
128
128
EEPROM -- Data Memory (bytes) Peripherals Timer Module(s) A/D Converter (8-bit) Channels Wake-up from SLEEP on pin change Interrupt Sources Features I/O Pins Input Pins Internal Pull-ups TMR0 --
--
16
16
--
--
16
16
TMR0 --
TMR0 --
TMR0 --
TMR0 4
TMR0 4
TMR0 4
TMR0 4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-- 5 1 Yes
-- 5 1 Yes Yes 5 1 Yes Yes 5 1 Yes Yes
4 5 1 Yes Yes
4 5 1 Yes Yes
4 5 1 Yes Yes
4 5 1 Yes Yes
In-Circuit Yes Serial Programming Number of Instructions Packages 33 8-pin DIP, JW, SOIC
33 8-pin DIP, JW, SOIC
33 8-pin DIP, JW, SOIC
33 8-pin DIP, JW, SOIC
35 8-pin DIP, JW, SOIC
35 8-pin DIP, JW, SOIC
35 8-pin DIP, JW
35 8-pin DIP, JW
All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.
DS40172B-page 4
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
2.0 PIC12CE5XX DEVICE VARIETIES
2.3 Quick-Turnaround-Production (QTP) Devices
A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12CE5XX Product Identification System at the back of this data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in windowed cerdip package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround Production (SQTPSM) Devices
Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.
Microchip's PICSTART(R) PLUS and PRO MATE(R) programmers all support programming of the PIC12CE5XX. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 5
PIC12CE5XX
NOTES:
DS40172B-page 6
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC12CE5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12CE5XX uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (1s @ 4MHz) except for program branches. The PIC12CE5XX can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC12CE5XX has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC12CE5XX simple yet efficient. In addition, the learning curve is reduced significantly. The PIC12CE5XX contains a 16 X 8 EEPROM memory array for storing non-volatile information such as calibration data or security codes. This memory has an endurance of 1,000,000 erase/write cycles and a retention of 40+ years. The table below lists program memory (EPROM), data memory (RAM), and non-volatile (EEPROM) for each PIC12CE5XX device. Device PIC12CE518 PIC12CE519 EPROM Program 512 x 12 1024 X 12 Memory RAM Data 25 x 8 41 X 8 EEPROM Data 16 x 8 16 X 8 The PIC12CE5XX device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 7
PIC12CE5XX
FIGURE 3-1: PIC12CE5XX BLOCK DIAGRAM
12 EPROM 512 x 12 or 1024 x 12 Program Memory Program 12 Bus Instruction reg Direct Addr 5 Program Counter 8 GPIO GP0 GP1 GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP5/OSC1/CLKIN SDA (c) 1998 Microchip Technology Inc. SCL Indirect Addr 16 X 8 EEPROM Data Memory
Data Bus
STACK1 STACK2
RAM 25 x 8 or 41 x 8 File Registers RAM Addr 9 Addr MUX 5-7
FSR reg 8 3 Device Reset Timer Instruction Decode & Control OSC1/CLKIN OSC2 Timing Generation Power-on Reset Watchdog Timer ALU 8 W reg STATUS reg
MUX
Internal RC OSC
MCLR VDD, VSS
Timer0
DS40172B-page 8
Preliminary
PIC12CE5XX
TABLE 3-1:
Name GP0
PIC12CE5XX PINOUT DESCRIPTION
DIP Pin # 7 SOIC Pin # 7 I/O/P Type I/O Buffer Type Description
TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. ST Bi-directional I/O port. Can be configured as T0CKI. TTL/ST Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pullup always on if configured as MCLR. Input buffers are Schmitt Trigger when configured in MCLR mode. TTL Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes).
GP1
6
6
I/O
GP2/T0CKI GP3/MCLR/VPP
5 4
5 4
I/O I
GP4/OSC2
3
3
I/O
GP5/OSC1/CLKIN
2
2
I/O
TTL/ST Bidirectional IO port/oscillator crystal input/external clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode. -- -- Positive supply for logic and I/O pins Ground reference for logic and I/O pins
VDD VSS
1 8
1 8
P P
Legend: I = input, O = output, I/O = input/output, P = power, -- = not used, TTL = TTL input, ST = Schmitt Trigger input
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 9
PIC12CE5XX
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1. An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Q1 Q2 Q3 Q4 PC
PC Fetch INST (PC) Execute INST (PC-1) PC+1 PC+2
Internal phase clock
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 03H 2. MOVWF GPIO 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
GPIO, BIT1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS40172B-page 10
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
4.0 MEMORY ORGANIZATION
FIGURE 4-1:
PIC12CE5XX memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC12CE519 with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).
PROGRAM MEMORY MAP AND STACK FOR THE PIC12CE5XX
PC<11:0> 12 Stack Level 1 Stack Level 2
CALL, RETLW
4.1
Program Memory Organization
Reset Vector (note 1)
0000h
The PIC12CE5XX devices have a 12-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Only the first 512 x 12 (0000h-01FFh) for the PIC12CE518 and 1K x 12 (0000h-03FFh) for the PIC12CE519 are physically implemented. Refer to Figure 4-1. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 12 space (PIC12CE518) or 1K x 12 space (PIC12CE519). The effective reset vector is at 000h, (see Figure 4-1). Location 01FFh (PIC12CE518) or location 03FFh (PIC12CE519), the hardwired reset vector location, contains the internal clock oscillator calibration value. This value is set at Microchip and should never be overwritten. Upon reset, the MOVLW XX is executed, the PC wraps to location 0000h, thus making 0000h the effective reset vector.
User Memory Space
On-chip Program Memory
512 Word (PIC12CE518)
01FFh 0200h
On-chip Program Memory
1024 Word (PIC12CE519)
03FFh 0400h
7FFh
Note 1: Address 0000h becomes the effective reset vector. Location 01FFh (PIC12CE518) or location 03FFh (PIC12CE519) contains the MOVLW XX INTRC oscillator calibration value.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 11
PIC12CE5XX
4.2 Data Memory Organization FIGURE 4-2:
Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the PIC12CE518, the register file is composed of 7 special function registers and 25 general purpose registers (Figure 4-2). For the PIC12CE519, the register file is composed of 7 special function registers, 41 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (Figure 4-3). 4.2.1 GENERAL PURPOSE REGISTER FILE
PIC12CE518 REGISTER FILE MAP
File Address 00h 01h 02h 03h 04h 05h 06h 07h INDF(1) TMR0 PCL STATUS FSR OSCCAL GPIO
General Purpose Registers
1Fh Note 1: Not a physical register. See Indirect Data Addressing, Section 4.8.
The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section 4.8).
FIGURE 4-3:
PIC12CE519 REGISTER FILE MAP
FSR<6:5> File Address 00h 01h 02h 03h 04h 05h 06h 07h General Purpose Registers 0Fh 10h General Purpose Registers 1Fh Bank 0 3Fh Bank 1 2Fh 30h General Purpose Registers INDF(1) TMR0 PCL STATUS FSR OSCCAL GPIO Addresses map back to addresses in Bank 0. 20h 00 01
Note 1: Not a physical register. See Indirect Data Addressing, Section 4.8.
DS40172B-page 12
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The special registers can be classified into two sets. The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
TABLE 4-1:
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Value on Power-On Reset --11 1111 1111 1111 xxxx xxxx xxxx xxxx 1111 1111 TO PD Z DC C 0001 1xxx 111x xxxx 110x xxxx CAL1 GP3 CAL0 GP2 -- GP1 -- GP0 1000 00-11xx xxxx Value on all other Resets(2) --11 1111 1111 1111 uuuu uuuu uuuu uuuu 1111 1111 q00q quuu(3) 111u uuuu 11uu uuuu uuuu uu-11uu uuuu
Address N/A N/A 00h 01h 02h 03h 04h 04h 05h 06h
(1)
Name TRIS OPTION INDF TMR0 PCL STATUS FSR (12CE518) FSR (12CE519) OSCCAL GPIO
Bit 7
Bit 6
Bit 5 GP5
Bit 4 GP4
Bit 3 GP3
Bit 2 GP2
Bit 1 GP1
Bit 0 GP0
--
--
Contains control bits to configure Timer0, Timer0/WDT prescaler, wakeup on change, and weak pull-ups Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of PC GPWUF
--
PA0
Indirect data memory address pointer Indirect data memory address pointer CAL5 SCL CAL4 SDA CAL3 GP5 CAL2 GP4
Legend: Shaded boxes = unimplemented or unused, -- = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in Section 8.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 for an explanation of how to access these bits. Note 2: Other (non-power up) resets include external reset through MCLR, WDT, and wake-up on pin change reset. Note 3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 13
PIC12CE5XX
4.2.3 EEPROM DATA MEMORY The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. Refer to Section 6.0 on EEPROM Peripherals. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary.
4.3
STATUS Register
This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.
FIGURE 4-4:
R/W-0 GPWUF bit7 bit 7:
STATUS REGISTER (ADDRESS:03h)
R/W-0 PA0 5 R-1 TO 4 R-1 PD 3 R/W-x Z 2 R/W-x DC 1 R/W-x C bit0
R/W-0
--
6
R = Readable bit W = Writable bit - n = Value at POR reset
GPWUF: GPIO reset bit 1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset Unimplemented PA0: Program page preselect bits 1 = Page 1 (200h - 3FFh) - PIC12CE519 0 = Page 0 (000h - 1FFh) - PIC12CE518 and PIC12CE519 Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF 1 = A carry occurred 1 = A borrow did not occur 0 = A carry did not occur 0 = A borrow occurred RRF or RLF Load bit with LSB or MSB, respectively
bit 6: bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS40172B-page 14
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
4.4 OPTION Register
Note: If TRIS bit is set to `0', the wake-up on change and pull-up functions are disabled for that pin; i.e., note that TRIS overrides OPTION control of GPPU and GPWU. If the T0CS bit is set to `1', GP2 is forced to be an input even if TRIS GP2 = `0'. The OPTION register is a 8-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits.
Note:
FIGURE 4-5:
W-1 GPWU bit7
OPTION REGISTER
W-1 T0CS 5 W-1 T0SE 4 W-1 PSA 3 W-1 PS2 2 W-1 PS1 1 W-1 PS0 bit0
W-1 GPPU 6
W = Writable bit U = Unimplemented bit - n = Value at POR reset Reference Table 4-1 for other resets.
bit 7:
GPWU: Enable wake-up on pin change (GP0, GP1, GP3) 1 = Disabled 0 = Enabled GPPU: Enable weak pull-ups (GP0, GP1, GP3) 1 = Disabled 0 = Enabled T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4 T0SE: Timer0 source edge select bit 1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 PS2:PS0: Prescaler rate select bits Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0:
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 15
PIC12CE5XX
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration. Increasing the CAL value increases the frequency.
FIGURE 4-6:
R/W-1 CAL5 bit7
OSCCAL REGISTER (ADDRESS 05Fh)
R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 U-0 -- U-0 -- bit0
R/W-0 CAL4
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: CAL<5:0>: Calibration bit 1-0: unimplemented
DS40172B-page 16
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
4.6 Program Counter
4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 47). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-7). Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5. Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XX, the PC will roll over to location 00h, and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected. Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.
4.7
Stack
PIC12CE5XX devices have a 12-bit wide hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL are executed, only 's the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW's are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.
FIGURE 4-7:
LOADING OF PC BRANCH INSTRUCTIONS PIC12CE518/CE519
GOTO Instruction
11 10 PC 9 87 PCL 0
Instruction Word PA0 7 0
Note 1: There are no STATUS bits to indicate stack overflows or stack underflow conditions. Note 2: There are no instructions mnemonics called PUSH nor POP. These are actions that occur from the execution of the CALL and RETLW instructions.
STATUS
CALL or Modify PCL Instruction
11 10 PC 9 87 PCL 0
Instruction Word Reset to `0' PA0 7 0
STATUS
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 17
PIC12CE5XX
4.8 Indirect Data Addressing; INDF and FSR Registers EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
NEXT
EXAMPLE 4-1:
* * * *
INDIRECT ADDRESSING
movlw movwf clrf incf btfsc goto :
Register file 07 contains the value 10h Register file 08 contains the value 0Ah Load the value 07 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 08) * A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.
CONTINUE
The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC12CE518: Does not use banking. FSR<7:5> are unimplemented and read as '1's. PIC12CE519: Uses FSR<5>. Selects between bank 0 and bank 1. FSR<7:6> is unimplemented, read as '1' .
FIGURE 4-8:
DIRECT/INDIRECT ADDRESSING
Direct Addressing (FSR) 65 4 (opcode) 0 6 Indirect Addressing 5 4 (FSR) 0
bank select
location select 00 00h Addresses map back to addresses in Bank 0. Data Memory(1) 0Fh 10h 01
bank
location select
1Fh Bank 0
3Fh Bank 1(2)
Note 1: For register map detail see Section 4.2. Note 2: PIC12CE519 only
DS40172B-page 18
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
5.0 I/O PORT
5.3 I/O Interfacing
As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O pins independent of the pin's input/output modes. On RESET, all GPIO ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0) for pin control. Bits 6 and 7 (SDA and SCL) are used by the EEPROM peripheral. Refer to Section 6.0 for use of SDA and SCL. Please note that GP3 is an input only pin. The configuration word can set several I/O's to alternate functions. When acting as alternate functions the pins will read as `0' during port read. Pins GP0, GP1, and GP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled.
FIGURE 5-1:
Data Bus D WR Port
EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
Q Data Latch CK Q VDD P
5.2
TRIS Register
W Reg
N D TRIS Latch Q VSS Q
I/O pin(1)
The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and GP2 which may be controlled by the option register, see Figure 4-5. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. The TRIS registers are "write-only" and are set (output drivers disabled) upon RESET.
TRIS `f'
CK
Reset
(2)
RD Port Note 1: I/O pins have protection diodes to VDD and VSS. Note 2: See Table 3-1 for buffer type.
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on Power-On Reset --11 1111 PS1 DC GP1 PS0 C GP0 1111 1111 0001 1xxx 11xx xxxx Value on all other Resets --11 1111 1111 1111 q00q quuu(1) 11uu uuuu
Address N/A N/A 03H 06h
Name TRIS OPTION STATUS GPIO
Bit 7 -- GPWU GPWUF SCL
Bit 6 -- GPPU -- SDA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O control registers TOCS PA0 GP5 TOSE TO GP4 PSA PD GP3 PS2 Z GP2
Legend: Shaded cells not used by Port Registers, read as `0', -- = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in Section 8.7 for possible values. Note 1: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 19
PIC12CE5XX
5.4
5.4.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wiredand"). The resulting high output currents may damage the chip.
;Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs ; ; GPIO latch GPIO pins ; ---------- ---------BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ; ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High).
5.4.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
FIGURE 5-2:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched GP5:GP0 Port pin written here Instruction executed MOVWF GPIO (Write to GPIO) Port pin sampled here MOVF GPIO,W (Read GPIO) NOP MOVWF GPIO PC + 1 MOVF GPIO,W PC + 2 NOP PC + 3 NOP
This example shows a write to GPIO followed by a read from GPIO. Data setup time = (0.25 TCY - TPD) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS40172B-page 20
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
6.0 EEPROM PERIPHERAL OPERATION
read data from the EEPROM peripheral requires outputting a `1' on SDA placing it in high-Z state, where only the internal 100K pull-up is active on the SDA line. SDA: Built-in 100K (typical) pull-up to VDD Open-drain (pull-down only) Always an output Outputs a `1' on reset SCL: Full CMOS output Always an output Outputs a `1' on reset The following example requires: * Code Space: 77 words * RAM Space: 5 bytes (4 are overlayable) * Stack Levels:1 (The call to the function itself. The functions do not call any lower level functions.) * Timing: - WRITE_BYTE takes 328 cycles - READ_CURRENT takes 212 cycles - READ_RANDOM takes 416 cycles. * IO Pins: 0 (No external IO pins are used) This code must reside in the lower half of a page. The code achieves it's small size without additional calls through the use of a sequencing table. The table is a list of procedures that must be called in order. The table uses an ADDWF PCL,F instruction, effectively a computed goto, to sequence to the next procedure. However the ADDWF PCL,F instruction yields an 8 bit address, forcing the code to reside in the first 256 addresses of a page.
The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h). Unlike the GP0-GP5 that are connected to the I/O pins, SDA and SCL are only connected to the internal EEPROM peripheral. For most applications, all that is required is calls to the following functions:
; Byte_Write: Byte write routine ; Inputs: EEPROM Address EEADDR ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W ; ; Read_Current: Read EEPROM at address currently held by EE device. ; Inputs: NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W ; ; Read_Random: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W
The code for these functions is available on our website www.microchip.com. The code will be accessed by either including the source code FL51XINC.ASM or by linking FLASH5IX.ASM. It is very important to check the return codes when using these calls, and retry the operation if unsuccessful. Unsuccessful return codes occur when the EE dta memeory is busy with the previos write, which can take up to 4 mS. 6.0.1 SERIAL DATA
6.0.2
SERIAL CLOCK
This SCL input is used to synchronize the data transfer from and to the device.
6.1
BUS CHARACTERISTICS
The following bus protocol is to be used with the EEPROM data memory. * Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 6-1). 6.1.1 BUS NOT BUSY (A)
SDA is a bi-directional pin used to transfer addresses and data into and data out of the device. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. The EEPROM interface is a 2-wire bus protocol consisting of data (SDA) and a clock (SCL). Although these lines are mapped into the GPIO register, they are not accessible as external pins; only to the internal EEPROM peripheral. SDA and SCL operation is also slightly different than GPO-GP5 as listed below. Namely, to avoid code overhead in modifying the TRIS register, both SDA and SCL are always outputs. To
Both data and clock lines remain HIGH.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 21
PIC12CE5XX
6.1.2 START DATA TRANSFER (B) 6.1.5 ACKNOWLEDGE A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 6.1.3 STOP DATA TRANSFER (C) Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 6.1.4 DATA VALID (D) Acknowledge bits are not generated if an internal programming cycle is in progress.
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 6-2).
DS40172B-page 22
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
FIGURE 6-1:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(C) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
FIGURE 6-2:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL SDA
1
2
3
4
5
6
7
8
9
1
2
3
Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
6.2
Device Addressing
FIGURE 6-3:
CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the bus master transmits a control byte consisting of a slave address and a Read/Write bit that indicates what type of operation is to be performed. The slave address consists of a 4-bit device code (1010) followed by three don't care bits. The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. (Figure 6-3). The bus is monitored for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode.
Device Select Bits
Don't Care Bits 0 X X X R/W ACK
S
1
0
1
Slave Address Start Bit Acknowledge Bit
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 23
PIC12CE5XX
6.3
6.3.1
WRITE OPERATIONS
BYTE WRITE
6.4
ACKNOWLEDGE POLLING
Following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit (which is a logic low) are placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer. Only the lower four address bits are used by the device, and the upper four bits are don't cares. The address byte is acknowledgeable and the master device will then transmit the data word to be written into the addressed memory location. The memory acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time will not generate acknowledge signals (Figure 6-5). After a byte write command, the internal address counter will not be incremented and will point to the same address location that was just written. If a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command will abort and no data will be written. If more than 8 data bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full eight data bits have been transmitted, then the write command will abort and no data will be written. The EEPROM memory employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below minimum VDD. Byte write operations must be preceded and immediately followed by a bus not busy bus cycle where both SDA and SCL are held high.
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 6-4 for flow diagram.
FIGURE 6-4:
ACKNOWLEDGE POLLING FLOW
Send Write Command
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
FIGURE 6-5:
BUS ACTIVITY MASTER SDA LINE
BYTE WRITE
S T A R T S 1 0 1 CONTROL BYTE WORD ADDRESS DATA S T O P P A C K A C K
0
X
X
X
0 A C K
X
X
X
X
BUS ACTIVITY X = Don't Care Bit
DS40172B-page 24
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
6.5 READ OPERATIONs
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 6.5.1 CURRENT ADDRESS READ device as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. It will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (Figure 6-7). After this command, the internal address counter will point to the address location following the one that was just read. 6.5.3 SEQUENTIAL READ
It contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the device issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (Figure 6-6). 6.5.2 RANDOM READ
Sequential reads are initiated in the same way as a random read except that after the device transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the device to transmit the next sequentially addressed 8-bit word (Figure 6-8). To provide sequential reads, it contains an internal address pointer which is incremented by one at the completion of each read operation. This address pointer allows the entire memory contents to be serially read during one operation.
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the
FIGURE 6-6:
CURRENT ADDRESS READ
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T CONTROL BYTE S T O P
S 1 0 1 0 XXX 1
P
A C K DATA N O A C K
X = Don't Care Bit
FIGURE 6-7:
RANDOM READ
S T A R T CONTROL BYTE WORD ADDRESS (n)
XXXX
BUS ACTIVITY MASTER
S T A R T
CONTROL BYTE
S T O P
S 10 10XXX0
S 10 10XXX1
P
A C K DATA (n) N O A C K
SDA LINE
BUS ACTIVITY
X = Don't Care Bit
A C K
A C K
FIGURE 6-8:
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
SEQUENTIAL READ
CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P
P
A C K A C K A C K A C K N O A C K
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 25
PIC12CE5XX
NOTES:
DS40172B-page 26
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
7.0 TIMER0 MODULE AND TMR0 REGISTER
Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.1. The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 7.2 details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 7-1.
The Timer0 module has the following features: * 8-bit timer/counter register, TMR0 - Readable and writable * 8-bit software programmable prescaler * Internal or external clock select - Edge select for external clock Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register.
FIGURE 7-1:
GP2/T0CKI Pin
TIMER0 BLOCK DIAGRAM
Data bus FOSC/4 0 1 1 Programmable Prescaler(2) 0 PSout Sync with Internal Clocks 8 TMR0 reg
T0SE 3 T0CS(1) PS2, PS1, PS0(1) PSA(1)
PSout (2 TCY delay) Sync
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 7-5).
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 27
PIC12CE5XX
FIGURE 7-2:
PC (Program Counter) Instruction Fetch
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
Timer0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0+1
NT0+2
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
Read TMR0 reads NT0 + 2
FIGURE 7-3:
PC (Program Counter) Instruction Fetch Timer0 T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC MOVWF TMR0 PC+1 MOVF TMR0,W PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W PC+4 MOVF TMR0,W PC+5 MOVF TMR0,W PC+6
T0+1
NT0
NT0+1
T0
Instruction Execute
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on Power-On Reset Value on all other Resets
Address 01h N/A N/A
Name TMR0 OPTION TRIS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 - 8-bit real-time clock/counter GPWU
--
xxxx xxxx PS2 PS1 PS0 1111 1111 --11 1111
uuuu uuuu 1111 1111 --11 1111
GPPU
--
T0CS
T0SE
PSA
TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0
Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged,
DS40172B-page 28
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
7.1 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.1.1 EXTERNAL CLOCK SYNCHRONIZATION When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 7.1.2 TIMER0 INCREMENT DELAY
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-4). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-4 shows the delay from the external clock edge to the timer incrementing. 7.1.3 OPTION REGISTER EFFECT ON GP2 TRIS
If the option register is set to read TIMER0 from the pin, the port is forced to an input regardless of the TRIS register setting.
FIGURE 7-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler Output (2) (1) External Clock/Prescaler Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (3)
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 29
PIC12CE5XX
7.2 Prescaler EXAMPLE 7-1:
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 8.6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's. 7.2.1 SWITCHING PRESCALER ASSIGNMENT
OPTION
CHANGING PRESCALER (TIMER0WDT)
1.CLRWDT ;Clear WDT 2.CLRF TMR0 ;Clear TMR0 & Prescaler 3.MOVLW '00xx1111'b; ;These 3 lines (5, 6, 7) 4.OPTION ; are required only if ; desired 5.CLRWDT ;PS<2:0> are 000 or 001 6.MOVLW '00xx1xxx'b ;Set Postscaler to 7.OPTION ; desired WDT rate
To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.
EXAMPLE 7-2:
CLRWDT MOVLW
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source
'xxxx0xxx'
The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.
FIGURE 7-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
TCY ( = Fosc/4) 0 1 M U X 1 0 T0SE M U X Sync 2 Cycles TMR0 reg 8
GP2/T0CKI Pin
T0CS
PSA
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA WDT Enable bit 0 MUX 1 PSA
WDT Time-Out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS40172B-page 30
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
8.0 SPECIAL FEATURES OF THE CPU
The PIC12CE5XX has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. If using INTRC or EXTRC there is an 18 ms delay only on VDD power-up. With this timer on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC12C5XX family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: * Oscillator selection * Reset - Power-On Reset (POR) - Device Reset Timer (DRT) - Wake-up from SLEEP on pin change * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit Serial Programming
8.1
Configuration Bits
The PIC12CE5XX configuration word consists of 5 bits. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the MCLR enable bit. One bit is the code protection bit (Figure 8-1).
FIGURE 8-1:
-- bit11 bit 4: -- 10
CONFIGURATION WORD FOR PIC12CE5XX
-- 9 -- 8 -- 7 -- 6 -- 5 MCLRE 4 CP 3 WDTE FOSC1 FOSC0 2 1 bit0 Register: Address(1): CONFIG FFFh
bit 11-5: Unimplemented MCLRE: MCLR enable bit. 1 = MCLR pin enabled 0 = MCLR tied to VDD, (Internally) CP: Code protection bit. 1 = Code protection off 0 = Code protection on WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator selection bits 11 = EXTRC - external RC oscillator 10 = INTRC - internal RC oscillator 01 = XT oscillator 00 = LP oscillator
bit 3:
bit 2:
bit 1-0:
Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word. This register is not user addressable during device operation. Refer to In-Circuit Serial ProgrammingTM Guide, (DS30277).
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 31
PIC12CE5XX
8.2
8.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 8-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC12CE5XX
Cap. Range C1 Cap. Range C2
The PIC12CE5XX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: * * * * LP: XT: INTRC: EXTRC: Low Power Crystal Crystal/Resonator Internal 4 MHz Oscillator External Resistor/Capacitor
Osc Type
Resonator Freq
XT 4.0 MHz 30 pF 30 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
TABLE 8-2:
8.2.2
CRYSTAL OSCILLATOR / CERAMIC RESONATORS Osc Type LP XT
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR PIC12CE5XX
Cap.Range C1 Cap. Range C2
In XT or LP modes, a crystal or ceramic resonator is connected to the GP5/OSC1/CLKIN and GP4/OSC2 pins to establish oscillation (Figure 8-2). The PIC12CE5XX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT or LP modes, the device can have an external clock source drive the GP5/ OSC1/CLKIN pin (Figure 8-3).
Resonator Freq
FIGURE 8-2:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (XT OR LP OSC CONFIGURATION)
OSC1
15 pF 15 pF 32 kHz(1) 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF Note 1: For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
C1(1)
PIC12CE5XX
SLEEP
XTAL RS(2) C2(1) OSC2
RF(3)
To internal logic
Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF approximate value = 10 M.
FIGURE 8-3:
EXTERNAL CLOCK INPUT OPERATION (XT OR LP OSC CONFIGURATION)
OSC1 PIC12CE5XX
Clock from ext. system Open
OSC2
DS40172B-page 32
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 8.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 8-6 shows how the R/C combination is connected to the PIC12CE5XX. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values.
Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 8-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.
FIGURE 8-4:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices
+5V 10k 4.7k 74AS04 74AS04 PIC12CE5XX CLKIN
10k XTAL 10k 20 pF 20 pF
Figure 8-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 8-6:
VDD Rext
EXTERNAL RC OSCILLATOR MODE
FIGURE 8-5:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
330 74AS04 To Other Devices 74AS04 PIC12CE5XX CLKIN
OSC1 N
Internal clock
Cext VSS
330 74AS04 0.1 F XTAL
PIC12CE5XX
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 33
PIC12CE5XX
8.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25C, see "Electrical Specifications" section for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the top of memory which contains the calibration value for the internal RC oscillator. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the reset vector. This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will "trim" the internal oscillator to remove process variation from the oscillator frequency. . Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part. Some registers are not reset in any way; they are unknown on POR and unchanged in any other reset. Most other registers are reset to "reset state" on poweron reset (POR), on MCLR, WDT or wake-up on pin change reset during normal operation. They are not affected by a WDT reset during SLEEP or MCLR reset during SLEEP, since these resets are viewed as resumption of normal operation. The exceptions to this are TO, PD, and GPWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the nature of reset. See Table 8-3 for a full description of reset states of all registers.
For the PIC12CE518 and PIC12CE519, bits <5:0>, CAL5-CAL0 are used for calibration. Adjusting CAL5-0 from 000000 to 111111 yields a higher clock speed. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices. For the PIC12CE518 and PIC12CE519, the lower 2 bits of the register are used to allow for future, longer bit length calibration schemes. Writing a larger value in this location yields a higher clock speed.
8.3
RESET
The device differentiates between various kinds of reset: a) Power on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP f) Wake-up from SLEEP on pin change
DS40172B-page 34
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
TABLE 8-3: RESET CONDITIONS FOR REGISTERS
Address -- 00h 01h 02h 03h 04h 04h 05h 06h -- -- Power-on Reset qqqq qqxx(1) xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 111x xxxx 110x xxxx 1000 00-11xx xxxx 1111 1111 --11 1111 MCLR Reset WDT time-out Wake-up on Pin Change qqqq qquu(1) uuuu uuuu uuuu uuuu 1111 1111 q00q quuu(3)(2) 111u uuuu 11uu uuuu uuuu uu-11uu uuuu 1111 1111 --11 1111
Register W INDF TMR0 PC STATUS FSR (12CE518) FSR (12CE519) OSCCAL GPIO OPTION TRIS
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. Note 2: See Table 8-7 for reset value for specific conditions. Note 3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.
TABLE 8-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h PCL Addr: 02h 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
Power on reset MCLR reset during normal operation MCLR reset during SLEEP WDT reset during SLEEP WDT reset normal operation Wake-up from SLEEP on pin change
0001 1xxx 000u uuuu 0001 0uuu 0000 0uuu 0000 uuuu 1001 0uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0'.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 35
PIC12CE5XX
8.3.1 MCLR ENABLE This configuration bit when unprogrammed (left in the `1' state) enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD, and the pin is assigned to be a GPIO. See Figure 8-7. When pin GP3/MCLR/VPP is configured as MCLR, the internal pull-up is always on. The Power-On Reset circuit and the Device Reset Timer (Section 8.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the onchip reset signal. A power-up example where MCLR is held low is shown in Figure 8-9. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. In Figure 8-10, the on-chip Power-On Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be GP3.). The VDD is stable before the start-up timer times out and there is no problem in getting a proper reset. However, Figure 811 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 8-10). Note: When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.
FIGURE 8-7:
MCLR SELECT
MCLRE WEAK PULL-UP GP3/MCLR/VPP INTERNAL MCLR
8.4
Power-On Reset (POR)
The PIC12CE5XX family incorporates on-chip PowerOn Reset (POR) circuitry which provides an internal chip reset for most power-up situations. The on chip POR circuit holds the chip in reset until Vdd has reached a high enough level for proper operation. To take advantage of the internal POR, program the GP3/MCLR/VPP pin as MCLR and tie through a resistor to VDD or program the pin as GP3. An internal weak pull-up resistor is implemented using a transistor. Refer to Table 11-1 for the pull-up resistor ranges. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating parameters are met. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 8-8.
For additional information refer to Application Notes "Power-Up Considerations" - AN522 and "Power-up Trouble Shooting" - AN607.
DS40172B-page 36
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up Detect VDD POR (Power-On Reset) Pin Change SLEEP GP3/MCLR/VPP Wake-up on pin change
WDT Time-out MCLRE 8-bit Asynch Ripple Counter (Start-Up Timer) RESET On-Chip DRT OSC
S
Q
R
Q
CHIP RESET
FIGURE 8-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT
INTERNAL RESET
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 37
PIC12CE5XX
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1 VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT
INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
8.5
Device Reset Timer (DRT)
TABLE 8-5:
Oscillator Configuration IntRC & ExtRC XT & LP
In the PIC12CE5XX, DRT runs from RESET and varies based on oscillator selection (see Table 8-5.) The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR has reached a logic high level. Thus, programming GP3/MCLR/VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the GP3/MCLR/VPP pin as a general purpose input. The Device Reset time delay will vary from chip to chip due to VDD, temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake from SLEEP mode automatically.
DRT (DEVICE RESET TIMER PERIOD)
POR Reset 18 ms (typical) 18 ms (typical) Subsequent Resets 300 s (typical) 18 ms (typical)
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external RC oscillator of the GP5/OSC1/CLKIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a '0' (Section 8.1). Refer to the PIC12CE5XX Programming Specifications to determine how to access the configuration word.
DS40172B-page 38
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
8.6.1 WDT PERIOD 8.6.2 WDT PROGRAMMING CONSIDERATIONS The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-topart process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., WDT prescaler = Max.), it may take several seconds before a WDT time-out occurs. The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset.
FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source (Figure 7-5)
0 Watchdog Timer 1 M U X Postscaler Postscaler
8 - to - 1 MUX WDT Enable Configuration Bit PSA
PS2:PS0
To Timer0 (Figure 7-4) 0 MUX Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. WDT Time-out 1 PSA
TABLE 8-6:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on Power-On Reset 1111 1111 Value on all other Resets 1111 1111
Address N/A
Name OPTION
Bit 7 GPWU
Bit 6 GPPU
Bit 5 T0CS
Bit 4 T0SE
Bit 3 PSA
Bit 2 PS2
Bit 1 Bit 0 PS1 PS0
Legend: Shaded boxes = Not used by Watchdog Timer, -- = unimplemented, read as '0', u = unchanged
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 39
PIC12CE5XX
8.7 Time-Out Sequence, Power Down, and Wake-up from SLEEP Status Bits (TO/PD/GPWUF) 8.8 Reset on Brown-Out
A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC12CE5XX devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 8-13 and Figure 8-14.
The TO, PD, and GPWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) reset.
TABLE 8-7:
GPWUF TO
0 0 0 0 0 1 Legend: 0 0 1 1 u 1
TO/PD/GPWUF STATUS AFTER RESET
PD
0 u 0 1 u 0
RESET caused by WDT wake-up from SLEEP WDT time-out (not from SLEEP) MCLR wake-up from SLEEP Power-up MCLR not during SLEEP Wake-up from SLEEP on pin change
FIGURE 8-13: BROWN-OUT PROTECTION CIRCUIT 1
VDD VDD Q1 MCLR 40k* PIC12CE5XX
33k 10k
Legend: u = unchanged Note 1: The TO, PD, and GPWUF bits maintain their status (u) until a reset occurs. A low-pulse on the MCLR input does not change the TO, PD, and GPWUF status bits.
This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). *Refer to Figure 8-7 and Table 11-1 for internal weak pullup on MCLR.
Table 8-4 lists the reset conditions for the special function registers, while Table 8-3 lists the reset conditions for all the registers.
FIGURE 8-14: BROWN-OUT PROTECTION CIRCUIT 2
VDD VDD R1 Q1 MCLR R2 40k PIC12CE5XX
This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD * R1 R1 + R2 = 0.7V
*Refer to Figure 8-7 and Table 11-1 for internal weak pull-up on MCLR.
DS40172B-page 40
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
8.9 Power-Down Mode (SLEEP) 8.10 Program Verification/Code Protection
A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 8.9.1 SLEEP If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations can be read regardless of the code protection bit setting. Note: The location containing the pre-programmed internal RC oscillator calibration value is never code protected.
The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the GP3/ MCLR/VPP pin must be at a logic high level if MCLR is enabled. 8.9.2 WAKE-UP FROM SLEEP
8.11
ID Locations
Four memory locations are designated as ID locations where the user can store checksum or other codeidentification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as '0's.
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. An external reset input on GP3/MCLR/VPP pin, when configured as MCLR. A Watchdog Timer time-out reset (if WDT was enabled). A change on input pin GP0, GP1, or GP3/ MCLR/VPP when wake-up on change is enabled.
These events cause a device reset. The TO, PD, and GPWUF bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The GPWUF bit indicates a change in state while in SLEEP at pins GP0, GP1, or GP3 (since the last time there was a file or bit operation on GP port). Caution: Right before entering SLEEP, read the input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake up will occur immediately even if no pins change while in SLEEP mode. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 41
PIC12CE5XX
8.12 In-Circuit Serial ProgrammingTM
The PIC12CE5XX microcontrollers program memory can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the GP1 and GP0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). GP1 becomes the programming clock and GP0 becomes the programming data. Both GP1 and GP0 are Schmitt Trigger inputs in this mode. After reset, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC12CE5XX Programming Specifications in the In-Circuit Serial Programming Guide, (DS30277). A typical in-circuit serial programming connection is shown in Figure 8-15.
FIGURE 8-15: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC12CE5XX VDD VSS MCLR/VPP GP1 GP0 VDD To Normal Connections
External Connector Signals +5V 0V VPP CLK Data I/O
DS40172B-page 42
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
9.0 INSTRUCTION SET SUMMARY
Each PIC12CE5XX instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC12CE5XX instruction set summary in Table 9-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator is used to specify which one of the 32 file registers is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Figure 9-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where 'h' signifies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR INSTRUCTIONS
6 5 d 4 f (FILE #) 0
Byte-oriented file register operations 11 OPCODE
d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 87 54 b (BIT #) f (FILE #) 0
TABLE 9-1:
Field
f W b k
OPCODE FIELD DESCRIPTIONS
Description
b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 OPCODE k = 8-bit immediate value Literal and control operations - GOTO instruction 11 OPCODE k = 9-bit immediate value 9 8 k (literal) 0 8 7 k (literal) 0
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0 (store result in W) d = 1 (store result in file register 'f') Default is d = 1 Label name Top of Stack Program Counter Watchdog Timer Counter Time-Out bit Power-Down bit Destination, either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
x
d
label TOS PC WDT TO PD
dest [] () <>
italics
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 43
PIC12CE5XX
TABLE 9-2:
Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ANDLW CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW f,d f,d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f, b f, b f, b f, b k k k k k k - k - f k
INSTRUCTION SET SUMMARY
12-Bit Opcode Description Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Swap f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set AND literal with W Call subroutine Clear Watchdog Timer Unconditional branch Inclusive OR Literal with W Move Literal to W Load OPTION register Return, place Literal in W Go into standby mode Load TRIS register Exclusive OR Literal to W Cycles MSb 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 2 1 2 1 1 1 2 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df LSb ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff Status Affected Notes C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z None None None None Z None TO, PD None Z None None None TO, PD None Z 1,2,4 2,4 4
2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 2,4 2,4
BIT-ORIENTED FILE REGISTER OPERATIONS 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff
LITERAL AND CONTROL OPERATIONS 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk 1
3
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO. (Section 4-5) 2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of GPIO. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).
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(c) 1998 Microchip Technology Inc.
PIC12CE5XX
ADDWF Syntax: Operands: Operation: Encoding: Description: Add W and f [ label ] ADDWF 0 f 31 d [0,1] (W) + (f) (dest)
0001 11df ffff
ANDWF f,d Syntax: Operands: Operation: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 31 d [0,1] (W) .AND. (f) (dest)
0001 01df ffff
f,d
Status Affected: C, DC, Z
Add the contents of the W register and register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'.
Status Affected: Z
The contents of the W register are AND'ed with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'.
Words: Cycles: Example:
W = FSR = W = FSR =
1 1
ADDWF 0x17 0xC2 0xD9 0xC2 FSR, 0
Words: Cycles: Example:
W= FSR = W = FSR =
1 1
ANDWF 0x17 0xC2 0x17 0x02 FSR, 1
Before Instruction
Before Instruction
After Instruction
After Instruction
ANDLW Syntax: Operands: Operation: Encoding: Description:
And literal with W [ label ] ANDLW 0 k 255 (W).AND. (k) (W) k
BCF Syntax: Operands: Operation:
Bit Clear f [ label ] BCF 0 f 31 0b7 0 (f)
0100 bbbf ffff
f,b
Status Affected: Z
1110 kkkk kkkk The contents of the W register are AND'ed with the eight-bit literal 'k'. The result is placed in the W register.
Status Affected: None Encoding: Description: Words: Cycles: Example: 1 1
BCF FLAG_REG, 7 Bit 'b' in register 'f' is cleared.
Words: Cycles: Example:
W W = =
1 1
ANDLW 0xA3 0x03 0x5F
Before Instruction
FLAG_REG = 0xC7
Before Instruction After Instruction
After Instruction
FLAG_REG = 0x47
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 45
PIC12CE5XX
BSF Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example: 1 1
BSF FLAG_REG, 7
Bit Set f [ label ] BSF 0 f 31 0b7 1 (f)
0101 bbbf ffff
BTFSS f,b Syntax: Operands: Operation: Encoding: Description:
Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 31 0b<7 skip if (f) = 1
0111 bbbf ffff
Status Affected: None
Bit 'b' in register 'f' is set.
Status Affected: None
If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and an NOP is executed instead, making this a 2 cycle instruction.
Before Instruction
FLAG_REG = 0x0A
Words: Cycles: Example:
1 1(2)
HERE FALSE TRUE * * BTFSS GOTO * FLAG,1 PROCESS_CODE
After Instruction
FLAG_REG = 0x8A
BTFSC Syntax: Operands: Operation: Encoding: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 31 0b7 skip if (f) = 0 0110
bbbf ffff
Before Instruction
PC = = = = = address (HERE) 0, address (FALSE); 1, address (TRUE)
After Instruction
If FLAG<1> PC if FLAG<1> PC
Status Affected: None
If bit 'b' in register 'f' is 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and an NOP is executed instead, making this a 2 cycle instruction.
Words: Cycles: Example:
1 1(2)
HERE FALSE TRUE BTFSC GOTO
FLAG,1 PROCESS_CODE
* * *
address (HERE) 0, address (TRUE); 1, address(FALSE)
Before Instruction
PC = = = = =
After Instruction
if FLAG<1> PC if FLAG<1> PC
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
CALL Syntax: Operands: Operation: Subroutine Call [ label ] CALL k 0 k 255 (PC) + 1 Top of Stack; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8>
1001 kkkk kkkk
CLRW Syntax: Operands: Operation:
Clear W [ label ] CLRW None 00h (W); 1Z
0000 0100 0000
Status Affected: Z Encoding: Description: Words: Cycles: Example:
W W Z = = = The W register is cleared. Zero bit (Z) is set.
Status Affected: None Encoding: Description:
Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two cycle instruction.
1 1
CLRW 0x5A 0x00 1
Before Instruction After Instruction
Words: Cycles: Example:
PC = PC = TOS =
1 2
HERE CALL THERE
Before Instruction
address (HERE) address (THERE) address (HERE + 1)
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD
0000 0000 0100
After Instruction
CLRF Syntax: Operands: Operation:
Clear f [ label ] CLRF 0 f 31 00h (f); 1Z
0000 011f ffff
f
Status Affected: TO, PD Encoding: Description:
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set.
Status Affected: Z Encoding: Description: Words: Cycles: Example:
The contents of register 'f' are cleared and the Z bit is set.
Words: Cycles: Example:
1 1
CLRWDT ? 0x00 0 1 1
1 1
CLRF = = = FLAG_REG 0x5A 0x00 1
Before Instruction
WDT counter =
Before Instruction
FLAG_REG
After Instruction
WDT counter WDT prescale TO PD = = = =
After Instruction
FLAG_REG Z
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 47
PIC12CE5XX
COMF Syntax: Operands: Operation: Encoding: Description: Complement f [ label ] COMF 0 f 31 d [0,1] (f) (dest)
0010 01df ffff
DECFSZ f,d Syntax: Operands: Operation: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 31 d [0,1] (f) - 1 d;
0010
skip if result = 0
ffff
Status Affected: Z
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: None
11df The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded and an NOP is executed instead making it a two cycle instruction.
Words: Cycles: Example:
REG1 REG1 W
1 1
COMF = = = 0x13 0x13 0xEC REG1,0
Before Instruction After Instruction
Words: Cycles: Example:
1 1(2)
HERE DECFSZ GOTO CONTINUE * * * = = = = = address (HERE) CNT - 1; 0, address (CONTINUE); 0, address (HERE+1) CNT, 1 LOOP
DECF Syntax: Operands: Operation: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 31 d [0,1] (f) - 1 (dest)
0000 11df ffff
Before Instruction
PC CNT if CNT PC if CNT PC
After Instruction
Status Affected: Z
Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
GOTO Syntax: Operands: Operation:
Unconditional Branch [ label ] GOTO k 0 k 511 k PC<8:0>; STATUS<6:5> PC<10:9>
101k kkkk kkkk
Words: Cycles: Example:
CNT Z CNT Z
1 1
DECF = = = = 0x01 0 0x00 1 CNT,
1
Before Instruction
Status Affected: None Encoding: Description:
GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a two cycle instruction.
After Instruction
Words: Cycles: Example:
PC =
1 2
GOTO THERE address (THERE)
After Instruction
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Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
INCF Syntax: Operands: Operation: Encoding: Description: Increment f [ label ] 0 f 31 d [0,1] (f) + 1 (dest)
0010 10df ffff
IORLW Syntax: Operands: Operation: Encoding: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W)
1101 kkkk kkkk
INCF f,d
Status Affected: Z
The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W register.
Status Affected: Z
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
Words: Cycles: Example:
1 1
IORLW = = = 0x9A 0xBF 0 0x35
Words: Cycles: Example:
CNT Z CNT Z
1 1
INCF = = = = CNT,
1
Before Instruction
W W Z
Before Instruction
0xFF 0 0x00 1
After Instruction
After Instruction IORWF Syntax: INCFSZ Syntax: Operands: Operation: Encoding: Description: Increment f, Skip if 0 [ label ] 0 f 31 d [0,1] (f) + 1 (dest), skip if result = 0
0011 11df ffff
Inclusive OR W with f [ label ] 0 f 31 d [0,1] (W).OR. (f) (dest)
0001 00df ffff
IORWF
f,d
Operands: Operation: Encoding: Description:
INCFSZ f,d
Status Affected: Z
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
Status Affected: None
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, then the next instruction, which is already fetched, is discarded and an NOP is executed instead making it a two cycle instruction.
Words: Cycles: Example:
1 1
IORWF 0x13 0x91 0x13 0x93 0 RESULT, 0
Before Instruction
RESULT = W =
Words: Cycles: Example:
1 1(2)
HERE INCFSZ GOTO CONTINUE * * * = = = = = address (HERE) CNT + 1; 0, address (CONTINUE); 0, address (HERE +1) CNT, LOOP 1
After Instruction
RESULT = W = Z =
Before Instruction
PC CNT if CNT PC if CNT PC
After Instruction
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 49
PIC12CE5XX
MOVF Syntax: Operands: Operation: Encoding: Description: Move f [ label ] 0 f 31 d [0,1] (f) (dest)
0010 00df ffff
MOVWF MOVF f,d Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example:
Move W to f [ label ] 0 f 31 (W) (f)
0000 001f ffff
MOVWF
f
Status Affected: None
Move data from the W register to register 'f'.
Status Affected: Z
The contents of register 'f' is moved to destination 'd'. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test a file register since status flag Z is affected.
1 1
MOVWF = = = = TEMP_REG 0xFF 0x4F 0x4F 0x4F
Words: Cycles: Example:
W =
1 1
MOVF FSR, 0
Before Instruction
TEMP_REG W
After Instruction
TEMP_REG W
After Instruction
value in FSR register
NOP MOVLW Syntax: Operands: Operation: Encoding: Description: Move Literal to W [ label ] k (W)
1100 kkkk kkkk
No Operation [ label ] None No operation
0000 0000 0000
Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example:
NOP
MOVLW k
0 k 255
Status Affected: None No operation. 1 1
NOP
Status Affected: None
The eight bit literal 'k' is loaded into the W register. The don't cares will assemble as 0s.
Words: Cycles: Example:
W =
1 1
MOVLW 0x5A 0x5A
After Instruction
DS40172B-page 50
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
OPTION Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example
W
Load OPTION Register [ label ] None (W) OPTION OPTION
RLF Syntax: Operands: Operation:
Rotate Left f through Carry [ label ] RLF 0 f 31 d [0,1] See description below
0011 01df ffff
f,d
Status Affected: None
0000 0000 0010 The content of the W register is loaded into the OPTION register.
Status Affected: C Encoding: Description:
The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'.
1 1
OPTION
Before Instruction
= 0x07 0x07
C Words: Cycles: Example: 1 1
RLF = = = = =
register 'f'
After Instruction
OPTION =
REG1,0 1110 0110 0 1110 0110 1100 1100 1
RETLW Syntax: Operands: Operation:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC
1000 kkkk kkkk
Before Instruction
REG1 C REG1 W C
After Instruction
Status Affected: None Encoding: Description:
The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.
RRF Syntax: Operands: Operation: Encoding: Description:
Rotate Right f through Carry [ label ] 0 f 31 d [0,1] See description below
0011 00df ffff
RRF f,d
Words: Cycles: Example:
1 2
CALL TABLE ;W contains ;table offset ;value. * ;W now has table * ;value. * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table = = 0x07 value of k8
Status Affected: C
The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
TABLE
C Words: Cycles: Example:
REG1 C REG1 W C
register 'f'
1 1
RRF = = = = = REG1,0 1110 0110 0 1110 0110 0111 0011 0
Before Instruction
W W
Before Instruction
After Instruction
After Instruction
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 51
PIC12CE5XX
SLEEP Syntax: Operands: Operation: Enter SLEEP Mode [label] None 00h WDT; 0 WDT prescaler; 1 TO; 0 PD
0000 0000 0011
SUBWF Syntax: Operands: Operation: Encoding: Description:
Subtract W from f [label] SUBWF f,d 0 f 31 d [0,1] (f) - (W) (dest)
0000 10df ffff
SLEEP
Status Affected: C, DC, Z
Subtract (2's complement method) the W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: TO, PD, GPWUF Encoding: Description:
Time-out status bit (TO) is set. The power down status bit (PD) is cleared. GPWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See section on SLEEP for more details.
Words: Cycles: Example 1:
REG1 W C REG1 W C
1 1
SUBWF = = = = = = 3 2 ? 1 2 1 REG1, 1
Before Instruction
Words: Cycles: Example:
1 1 SLEEP
After Instruction
; result is positive
Example 2: Before Instruction
REG1 W C REG1 W C = = = = = = 2 2 ? 0 2 1
After Instruction
; result is zero
Example 3: Before Instruction
REG1 W C REG1 W C = = = = = = 1 2 ? FF 2 0
After Instruction
; result is negative
DS40172B-page 52
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
SWAPF Syntax: Operands: Operation: Swap Nibbles in f [ label ] SWAPF f,d 0 f 31 d [0,1] (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>)
0011 10df ffff
XORLW Syntax: Operands: Operation: Encoding: Description:
Exclusive OR literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W)
1111 kkkk kkkk
Status Affected: Z
The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register.
Status Affected: None Encoding: Description:
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: Cycles: Example:
1 1 XORLW
= = 0xB5 0x1A
Words: Cycles: Example
REG1 REG1 W
1 1
SWAPF = = =
0xAF
Before Instruction REG1, 0
W W
Before Instruction
0xA5 0xA5 0X5A
After Instruction
After Instruction XORWF Syntax: Operands: TRIS Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example
W TRIS
Exclusive OR W with f [ label ] XORWF 0 f 31 d [0,1] (W) .XOR. (f) (dest)
0001 10df ffff
f,d
Load TRIS Register [ label ] TRIS f=6 (W) TRIS register f
0000 0000 0fff
f
Operation: Encoding: Description:
Status Affected: Z
Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.
Status Affected: None
TRIS register 'f' (f = 6) is loaded with the contents of the W register
1 1
TRIS = = 0XA5 0XA5 GPIO
Words: Cycles: Example
REG W REG W
1 1 XORWF
= = = = REG,1
Before Instruction After Instruction Note: f = 6 for PIC12C5XX only.
Before Instruction
0xAF 0xB5 0x1A 0xB5
After Instruction
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 53
PIC12CE5XX
NOTES:
DS40172B-page 54
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
10.0
10.1
DEVELOPMENT SUPPORT
Development Tools
10.3
ICEPIC: Low-Cost PICmicroTM In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a full range of hardware and software development tools: * MPLABTM-ICE Real-Time In-Circuit Emulator * ICEPICTM Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * SIMICE * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C17 (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP) * KEELOQ(R) Evaluation Kits and Programmer
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through PentiumTM based machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation.
10.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
10.2
MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). MPLAB-ICE is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is available in two versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PICmicro MCU.
10.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 55
PIC12CE5XX
10.6 SIMICE Entry-Level Hardware Simulator 10.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip's simulator MPLABTM-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology's MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchip's PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicroTM 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entrylevel system development.
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
10.7
PICDEM-1 Low-Cost PICmicro Demonstration Board
10.9
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
DS40172B-page 56
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
10.10 MPLAB Integrated Development Environment Software 10.12 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
10.13
MPLAB-C17 Compiler
The MPLAB-C17 Code Development System is a complete ANSI `C' compiler and integrated development environment for Microchip's PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
10.14
Fuzzy Logic Development System (fuzzyTECH-MP)
10.11
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from MPLABICE, Microchip's Universal Emulator System. MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
10.15
SEEVAL(R) Evaluation and Programming System
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 57
PIC12CE5XX
10.16 KEELOQ(R) Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS40172B-page 58
Preliminary
(c) 1998 Microchip Technology Inc.
Software Tools
Programmers
Demo Boards
(c) 1998 Microchip Technology Inc.
TABLE 10-1:
PIC12C5XX Emulator Products
PIC14000
PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
MPLABTM-ICE
u
u
u
u
u
u
u
u
u
u
DEVELOPMENT TOOLS FROM MICROCHIP
ICEPICTM Low-Cost In-Circuit Emulator MPLABTM Integrated Development Environment MPLABTM C17* Compiler u u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
fuzzyTECH(R)-MP Explorer/Edition Fuzzy Logic Dev. Tool
Total EnduranceTM Software Model PICSTART(R)Plus Low-Cost Universal Dev. Kit PRO MATE(R) II Universal Programmer KEELOQ(R) Programmer SEEVAL(R) Designers Kit SIMICE PICDEM-14A PICDEM-1 PICDEM-2 PICDEM-3 KEELOQ(R) Evaluation Kit KEELOQ Transponder Kit
u
u
u
u
u
u
u
u
u
Preliminary
DS40172B-page 59
u u u u u u u u u u u
u
u
u
u
u
u
u
u
u
u
u
u u
PIC12CE5XX
u u u u u u u u u u u u u
PIC12CE5XX
NOTES:
DS40172B-page 60
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
11.0 ELECTRICAL CHARACTERISTICS - PIC12CE5XX
Absolute Maximum Ratings
Ambient Temperature under bias ........................................................................................................... -40C to +125C Storage Temperature.............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS .................................................................................................................0 to +7.0 V Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V Voltage on all other pins with respect to VSS ................................................................................-0.6 V to (VDD + 0.6 V) Total Power Dissipation(1) ....................................................................................................................................700 mW Max. Current out of VSS pin...................................................................................................................................200 mA Max. Current into VDD pin......................................................................................................................................150 mA Input Clamp Current, IIK (VI < 0 or VI > VDD) ....................................................................................................................20 mA Output Clamp Current, IOK (VO < 0 or VO > VDD) ............................................................................................................20 mA Max. Output Current sunk by any I/O pin ................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................25 mA Max. Output Current sourced by I/O port (GPIO)..................................................................................................100 mA Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
NOTICE:
Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 61
PIC12CE5XX
11.1 DC CHARACTERISTICS: PIC12CE518/519 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Sym VDD VDR VPOR SVDD 0.05* IDD -- -- D010A D013 -- -- -- D020 Power-Down Current (5) D021 D021A D021B Supply Current(3) During read/write to EEPROM peripheral Power-Down Current (5) IPD -- -- -- IEE -- 0.26 0.26 2 0.1 5 6 13 0.2 A A A mA VDD = 3.0V, Commercial VDD = 3.0V, Industrial VDD = 4.5V, Extended FOSC = 4 MHz, VDD = 5.5V, SCL = 400 kHz 1.8 1.8 15 19 19 Min 3.0 1.5* VSS Typ(1) Max 5.5 -- -- -- 2.4 2.4 27 35 35 Units V V V V/ms mA mA A A A Conditions FOSC = DC to 4 MHz Device in SLEEP mode See section on Power-on Reset for details See section on Power-on Reset for details XT and EXTRC options (Note 4) FOSC = 4 MHz, VDD = 5.5V INTRC Option FOSC = 4 MHz, VDD = 5.5V LP OPTION, Commercial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled LP OPTION, Industrial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled LP OPTION, Extended Temperature FOSC = 32 kHz, VDD = 4.5V, WDT disabled
DC Characteristics Power Supply Pins Parm No.
Characteristic
D001 Supply Voltage D001A D002 D003 D004 D010 RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(3)
IWDT -- -- -- 3.74 3.74 3.0 8 9 10
A A A
VDD = 3.0V, Commercial VDD = 3.0V, Industrial VDD = 4.5V, Extended
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. c) EEPROM data memory in standby unless otherwise indicated. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. EEPROM data memory in standby.
DS40172B-page 62
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
11.2 DC CHARACTERISTICS: PIC12LCE518/519 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Sym VDD VDR VPOR SVDD IDD 0.05* -- -- -- -- Power-Down Current (5) IPD -- -- Supply Current(3) During read/write to EEPROM peripheral IEE -- TBD TBD TBD TBD TBD TBD A A mA VDD = 2.5V, Commercial VDD = 2.5V, Industrial XT and EXTRC options (Note 4) FOSC = 4 MHz, VDD = 5.5V, SCL = 400 kHz INTRC Option FOSC = 4 MHz, VDD = 5.5V SCL = 400 kHz VDD = 2.5V, Commercial VDD = 2.5V, Industrial TBD TBD TBD TBD Min 2.5 -- 1.5* VSS Typ(1) Max 5.5 -- -- -- TBD TBD TBD TBD Units V V V V/ms mA mA A A Conditions FOSC = DC to 4 MHz (Commercial/ Industrial) Device in SLEEP mode See section on Power-on Reset for details See section on Power-on Reset for details XT and EXTRC options (Note 4) FOSC = 4 MHz, VDD = 5.5V INTRC Option FOSC = 4 MHz, VDD = 5.5V LP OPTION, Commercial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled LP OPTION, Industrial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled
DC Characteristics Power Supply Pins
Characteristic Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(3) No read/write to EEPROM peripheral
--
TBD
TBD
mA
Power-Down Current (5)
IWDT -- -- TBD TBD TBD TBD
A A
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. c) EEPROM data memory in standby unless otherwise indicated. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. EEPROM data memory in standby.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 63
PIC12CE5XX
11.3 DC CHARACTERISTICS: PIC12CE518/519 (Commercial, Industrial, Extended) Timing Parameter Symbology and Load Conditions
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VIH 2.0 0.8VDD 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 0.5V 0.2VDD 0.2VDD 0.3VDD V V V V Note1
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer
D030 D031 D032 D033
D040 D040A D041 D042 D042A D043 D070 D060 D061 D063
with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT OSC1 (XT, HS and LP) OSC1 (in EXTRC mode) GPIO weak pull-up current IPUR Input Leakage Current (Notes 2, 3) I/O ports IIL MCLR, GP2/T0CKI OSC1 Output Low Voltage I/O ports/CLKOUT
VDD VDD VDD VDD VDD VDD 400 +1 +5(5) +5
V V V V V V A
4.5 VDD 5.5V For VDD > 5.5V or VDD < 4.5V For entire VDD range Note1 VDD = 5V, VPIN = VSS
A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V
D080 D080A D083 D083A Note 1: 2: 3: 4: 5:
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C OSC2 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12CE5XX be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device. When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up.
VOL
-
-
0.6
DS40172B-page 64
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Sym Min Typ Max Units Conditions VOH VDD - 0.7 VDD - 0.7 OSC2 VDD - 0.7 VDD - 0.7 Capacitive Loading Specs on Output Pins OSC2 pin V V V V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C
Param No. D090 D090A D092 D092A
Characteristic Output High Voltage I/O ports/CLKOUT (Note 3)
D100
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 Note 1: 2: 3: 4: 5:
All I/O pins and OSC2 CIO 50 pF Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12CE5XX be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device. When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 65
PIC12CE5XX
11.4 DC CHARACTERISTICS: PIC12LCE518/519 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.1. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VIH 2.0 0.8VDD 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 0.5V 0.2VDD 0.2VDD 0.3VDD V V V V Note1
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer
D030 D031 D032 D033
D040 D040A D041 D042 D042A D043 D070 D060 D061 D063
with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT OSC1 (XT, HS and LP) OSC1 (in EXTRC mode) GPIO weak pull-up current IPUR Input Leakage Current (Notes 2, 3) I/O ports IIL MCLR, GP2/T0CKI OSC1 Output Low Voltage I/O ports/CLKOUT
VDD VDD VDD VDD VDD VDD 400 +1 +5(5) +5
V V V V V V A
4.5 VDD 5.5V For VDD > 5.5V or VDD < 4.5V For entire VDD range Note1 VDD = 5V, VPIN = VSS
A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V
D080 D080A D083 D083A Note 1: 2: 3: 4: 5:
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C OSC2 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12CE5XX be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device. When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up.
VOL
-
-
0.6
DS40172B-page 66
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.1. Sym Min Typ Max Units Conditions VOH VDD - 0.7 VDD - 0.7 OSC2 VDD - 0.7 VDD - 0.7 Capacitive Loading Specs on Output Pins OSC2 pin V V V V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C
Param No. D090 D090A D092 D092A
Characteristic Output High Voltage I/O ports/CLKOUT (Note 3)
D100
COSC2
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 Note 1: 2: 3: 4: 5:
All I/O pins and OSC2 CIO 50 pF Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12CE5XX be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Extended operating range is Advance Information for this device. When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum. This pull-up is weaker than the standard I/O pull-up.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 67
PIC12CE5XX
TABLE 11-1:
VDD (Volts) 2.5
PULL-UP RESISTOR RANGES
Temperature (C) -40 25 85 125 -40 25 85 125 -40 25 85 125 -40 25 85 125 Min GP0/GP1 38K 42K 42K 50K 15K 18K 19K 22K GP3 285K 343K 368K 431K 247K 288K 306K 351K 42K 48K 49K 55K 17K 20K 22K 24K 346K 414K 457K 504K 292K 341K 371K 407K 63K 63K 63K 63K 20K 23K 25K 28K 417K 532K 532K 593K 360K 437K 448K 500K Typ Max Units
5.5
2.5
5.5
*
These parameters are characterized but not tested.
DS40172B-page 68
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
11.5 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F pp 2 ck cy drt io S F H I L Fall High Invalid (Hi-impedance) Low P R V Z Period Rise Valid Hi-impedance to CLKOUT cycle time device reset timer I/O port mc osc os t0 wdt MCLR oscillator OSC1 T0CKI watchdog timer Frequency T Time Lowercase subscripts (pp) and their meanings:
Uppercase letters and their meanings:
FIGURE 11-1: LOAD CONDITIONS - PIC12CE5XX
Pin CL VSS
CL = 50 pF for all pins except OSC2 15 pF for OSC2 in XT or LP modes when external clock is used to drive OSC1
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 69
PIC12CE5XX
11.6 Timing Diagrams and Specifications FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12CE5XX
Q4 OSC1 1 2 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 11-2:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12CE5XX
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 11.1 Characteristic
External CLKIN Frequency(2) Oscillator Frequency
(2)
AC Characteristics
Parameter No.
Sym
FOSC
Min
DC DC DC 0.1 DC
Typ(1)
-- -- -- -- -- -- -- -- -- -- 4/FOSC -- -- -- --
Max
4 200 4 4 200 -- -- -- 10,000 -- -- -- -- 25* 50*
Units
Conditions
MHz XT osc mode kHz LP osc mode MHz EXTRC osc mode MHz XT osc mode kHz ns ms ns ns ms -- ns ms ns ns XT oscillator LP oscillator XT oscillator LP oscillator LP osc mode XT osc mode LP osc mode EXTRC osc mode XT osc mode LP osc mode
1
Tosc
External CLKIN Period Oscillator Period
(2)
(2)
250 5 250 250 5
2 3 4
Tcy
Instruction Cycle Time
(3)
-- 50* 2* -- --
TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time
* These parameters are characterized but not tested.
Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS40172B-page 70
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
TABLE 11-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12CE5XX
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1 Characteristic
Internal Calibrated RC Frequency Internal Calibrated RC Frequency * These parameters are characterized but not tested.
AC Characteristics
Parameter No.
Sym
Min* Typ(1)
TBD TBD 4.00 4.00
Max* Units
TBD TBD
Conditions
MHz VDD = 5.0V MHz VDD = 2.5V
Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 11-3:
I/O TIMING - PIC12CE5XX
Q4 Q1 Q2 Q3
OSC1
I/O Pin (input)
17 19 18 New Value 20, 21
I/O Pin (output)
Old Value
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 71
PIC12CE5XX
TABLE 11-4: TIMING REQUIREMENTS - PIC12CE5XX
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 11.1 Characteristic OSC1 (Q1 cycle) to Port out valid(3) OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time(3) Port output fall time(3) Min -- TBD TBD -- -- Typ(1) -- -- -- 10 10 Max 100* -- -- 25** 25** Units ns ns ns ns ns AC Characteristics
Parameter No. 17 18 19 20 21
Sym TosH2ioV TosH2ioI TioV2osH TioR TioF
* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 11-1 for loading conditions.
FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12CE5XX
VDD MCLR 30 Internal POR 32 DRT Timeout (Note 2) Internal RESET Watchdog Timer RESET 31 34 I/O pin (Note 1) 34
32
32
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT and LP modes.
DS40172B-page 72
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
TABLE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12CE5XX
AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 11.1 Parameter No.
30 31
Sym TmcL Twdt TDRT TioZ
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Device Reset Timer Period(2) I/O Hi-impedance from MCLR Low
Min 2000* 9* 9* --
Typ(1) -- 18* 18* --
Max -- 30* 30* 2000*
Units ns ms ms ns
Conditions VDD = 5 V VDD = 5 V (Commercial) VDD = 5 V (Commercial)
32 34
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 11-6:
DRT (DEVICE RESET TIMER PERIOD) TIME OUT
POR Reset 18 ms (typical) 18 ms (typical) Subsequent Resets 300 s (typical) 18 ms (typical)
Oscillator Configuration IntRC & ExtRC XT & LP
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 73
PIC12CE5XX
FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12CE5XX
T0CKI 40 41
42
TABLE 11-7:
TIMER0 CLOCK REQUIREMENTS - PIC12CE5XX
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section 11.1. Min
0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N
AC Characteristics
Parameter Sym Characteristic No.
40 Tt0H T0CKI High Pulse Width - No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width - No Prescaler - With Prescaler 42 Tt0P T0CKI Period
Typ(1) Max Units Conditions
-- -- -- -- -- -- -- -- -- -- ns ns ns ns ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 11-6: EEPROM MEMORY BUS TIMING DATA
TF SCL TSU:STA TLOW SDA IN TSP THD:STA TBUF TAA SDA OUT THD:DAT TSU:DAT TSU:STO THIGH TR
DS40172B-page 74
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
TABLE 11-8: EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE5XX
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C, Vcc = 3.0V to 5.5V (commercial) -40C TA +85C, Vcc = 3.0V to 5.5V (industrial) -40C TA +125C, Vcc = 4.5V to 5.5V (extended) Operating Voltage VDD range is described in Section 11.1 Symbol FCLK Min -- -- -- 4000 4000 600 4700 4700 1300 -- -- -- -- 4000 4000 600 4700 4700 600 0 250 250 100 4000 4000 600 -- -- -- 4700 4700 1300 20+0.1 CB -- -- 1M Max 100 100 400 -- -- -- -- -- -- 1000 1000 300 300 -- -- -- -- -- -- -- -- -- -- -- -- -- 3500 3500 900 -- -- -- 250 50 4 -- Units kHz Conditions 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V (Note 1) 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V (Note 2) 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V 4.5V Vcc 5.5V (E Temp range) 3.0V Vcc 4.5V 4.5V Vcc 5.5V (Note 1), CB 100 pF (Notes 1, 3) AC Characteristics
Parameter Clock frequency
Clock high time
THIGH
ns
Clock low time
TLOW
ns
SDA and SCL rise time (Note 1) SDA and SCL fall time START condition hold time
TR
ns
TF THD:STA
ns ns
START condition setup time
TSU:STA
ns
Data input hold time Data input setup time
THD:DAT TSU:DAT
ns ns
STOP condition setup time
TSU:STO
ns
Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance
TAA
ns
TBUF
ns
TOF TSP TWC
ns ns ms cycles
25C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip's website.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 75
PIC12CE5XX
NOTES:
DS40172B-page 76
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
12.0 DC AND AC CHARACTERISTICS - PIC12CE5XX
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation.
FIGURE 12-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
Not available at this time.
FIGURE 12-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 2.5V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
Not available at this time.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 77
PIC12CE5XX
TABLE 12-1:
Oscillator
DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25C
Frequency VDD =3.0V VDD = 5.5V 620 A* 1.1 mA 775 A 37 A
External RC 4 MHz 300 A* Internal RC 4 MHz 520 A XT 4 MHz 300 A LP 32 KHz 10 A *Does not include current through external R&C.
FIGURE 12-3: WDT TIMER TIME-OUT PERIOD vs. VDD
50
FIGURE 12-4: SHORT DRT PERIOD VS. VDD
1000 900
45 800 40 700 WDT period (s) WDT period (s) 35 30 600
500 400 300 200
25 20 15 10 5 2 3 4 5 VDD (Volts)
Max +125C Max +85C
Max +125C Max +85C Typ +25C
Typ +25C
MIn -40C
MIn -40C
100 2 6 7 3 4 5 VDD (Volts) 6 7
DS40172B-page 78
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
FIGURE 12-5: IOH vs. VOH, VDD = 2.5 V
0
FIGURE 12-6: IOL vs. VOL, VDD = 2.5 V
35
-5
30
-10
25
IOH (mA)
-15
IOL (mA)
TBD
20
TBD
-20
15
10
-25
5
-30 1.5 2.0 2.5 3.0 3.5
0 0 500.0m 750.0m 1.0 VOL (Volts)
VOH (Volts)
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 79
PIC12CE5XX
FIGURE 12-7: IOH vs. VOH, VDD = 3.5 V
0
FIGURE 12-9: IOL vs. VOL, VDD = 3.5 V
35
-5
30
-10
25
Mi n+ 1 C 25
IOH (mA)
-15
Mi
-20
Typ
5 +2
15
Ma
x-
C 40
10
-25
5
-30 1.5 2.0 2.5 3.0 3.5
0 0 500.0m 750.0m 1.0 VOL (Volts)
VOH (Volts)
FIGURE 12-8: IOH vs. VOH, VDD = 5.5 V FIGURE 12-10: IOL vs. VOL, VDD = 5.5 V
0
50
-5
Ty p
C
C C 5 +8 125 + M in M in
+2 5
n+
IOL (mA)
C
C 85
20
M
ax
-4
0
C
Max -40C
40
-10
IOH (mA)
30 IOL (mA)
-15
C
Typ +25C
in
+8 5
M
M
+2
5
C
C
-20
in
+1
25
20
Min +85C
Ty p
-25
-4 0 C
Min +125C
-30 3.5 4.0 4.5 5.0 5.5
M
10
ax
VOH (Volts)
0 250.0m 500.0m 750.0m 1.0 VOL (Volts)
DS40172B-page 80
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
13.0
13.1
PACKAGING INFORMATION
Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXCDE AABB Example 12CE518 04I/PSAZ 9825
8-Lead SOIC (150 mil) XXXXXXX XXXX 8-Lead SOIC (208 mil) XXXXXXX XXXXXXX AABBCDE
Example CE518 9825 Example 12CE518 04I/SM 9824SAZ
8-Lead Windowed Ceramic Side Brazed (300 mil) XXX
Example JW
XXXXXX
12CE518
Legend: MM...M XX...X AA BB C
D E Note:
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5" Line S = 6" Line H = 8" Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 81
PIC12CE5XX
Package Type: K04-018 8-Lead Plastic Dual In-line (P) - 300 mil
E
D 2 1 E1
n
A A1
R
c
L A2
eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
B1 p B INCHES* NOM 0.300 8 0.100 0.018 0.014 0.060 0.055 0.005 0.000 0.012 0.006 0.150 0.140 0.080 0.060 0.020 0.005 0.130 0.120 0.370 0.355 0.250 0.245 0.280 0.267 0.310 0.342 5 10 5 10 MILLIMETERS NOM MAX 7.62 8 2.54 0.56 0.36 0.46 1.65 1.40 1.52 0.25 0.00 0.13 0.38 0.20 0.29 4.06 3.56 3.81 2.54 1.52 2.03 0.89 0.13 0.51 3.56 3.05 3.30 9.78 9.02 9.40 6.60 6.22 6.35 7.42 6.78 7.10 7.87 8.67 9.65 5 10 15 5 10 15
MIN n p B B1 R c A A1 A2 L D E E1 eB
MAX
MIN
0.022 0.065 0.010 0.015 0.160 0.100 0.035 0.140 0.385 0.260 0.292 0.380 15 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS40172B-page 82
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
Package Type: K04-057 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil
E1 E
p D 2 B n 1
45
X
L c R2 A A1
R1 L1
A2
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
MIN p n A A1 A2 D E E1 X R1 R2 L L1 c B
INCHES* NOM 0.050 8 0.061 0.054 0.035 0.027 0.007 0.004 0.193 0.189 0.154 0.150 0.237 0.229 0.015 0.010 0.005 0.005 0.005 0.005 0.016 0.011 0 4 0.005 0.000 0.008 0.009 0.014 0.017 12 0 12 0
MAX
MIN
0.069 0.044 0.010 0.196 0.157 0.244 0.020 0.010 0.010 0.021 8 0.010 0.010 0.020 15 15
MILLIMETERS NOM MAX 1.27 8 1.56 1.37 1.75 0.69 0.90 1.11 0.10 0.18 0.25 4.80 4.89 4.98 3.81 3.90 3.99 5.82 6.01 6.20 0.25 0.38 0.51 0.13 0.13 0.25 0.13 0.13 0.25 0.28 0.41 0.53 8 0 4 0.00 0.13 0.25 0.22 0.25 0.19 0.36 0.43 0.51 0 12 15 0 12 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 83
PIC12CE5XX
Package Type: K04-056 8-Lead Plastic Small Outline (SM) - Medium, 208 mil
E1 E
p D 2 n B L c R2 A A1 1
R1 L1
A2
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
MIN p n A A1 A2 D E E1 R1 R2 L L1 c B
INCHES* NOM 0.050 8 0.070 0.074 0.037 0.042 0.002 0.005 0.200 0.205 0.203 0.208 0.313 0.300 0.005 0.005 0.005 0.005 0.016 0.011 0 4 0.015 0.010 0.008 0.009 0.014 0.017 0 12 12 0
MAX
MIN
0.079 0.048 0.009 0.210 0.213 0.325 0.010 0.010 0.021 8 0.020 0.010 0.020 15 15
MILLIMETERS NOM MAX 1.27 8 2.00 1.89 1.78 1.21 0.94 1.08 0.22 0.05 0.14 5.08 5.33 5.21 5.16 5.41 5.28 7.62 7.94 8.26 0.13 0.13 0.25 0.13 0.13 0.25 0.28 0.41 0.53 8 0 4 0.25 0.38 0.51 0.19 0.22 0.25 0.36 0.43 0.51 0 12 15 0 12 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B." Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS40172B-page 84
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
Package Type: K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) - 300 mil
E
W
T 2 n 1
D
U
A
A1
L A2 c eB B1 p B
Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Lead Thickness Top to Seating Plane Top of Body to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Overall Row Spacing Window Diameter Lid Length Lid Width * Controlling Parameter.
MIN n p B B1 c A A1 A2 L D E eB W T U
0.098 0.016 0.050 0.008 0.145 0.103 0.025 0.130 0.510 0.280 0.310 0.161 0.440 0.260
INCHES* NOM 0.300 8 0.100 0.018 0.055 0.010 0.165 0.123 0.035 0.140 0.520 0.290 0.338 0.166 0.450 0.270
MAX
MIN
0.102 0.020 0.060 0.012 0.185 0.143 0.045 0.150 0.530 0.300 0.365 0.171 0.460 0.280
MILLIMETERS NOM MAX 7.62 8 2.54 2.49 2.59 0.41 0.51 0.46 1.27 1.40 1.52 0.20 0.25 0.30 3.68 4.70 4.19 3.12 2.62 3.63 0.89 0.64 1.14 3.56 3.30 3.81 12.95 13.21 13.46 7.11 7.37 7.62 7.87 9.27 8.57 4.09 4.34 4.22 11.18 11.68 11.43 6.60 7.11 6.86
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 85
PIC12CE5XX
NOTES:
DS40172B-page 86
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
INDEX A
ALU ....................................................................................... 7 Applications........................................................................... 3 Architectural Overview .......................................................... 7 Assembler MPASM Assembler..................................................... 57
L
Loading of PC ..................................................................... 17
M
Memory Organization ......................................................... 11 Data Memory .............................................................. 12 Program Memory........................................................ 11 MPLAB Integrated Development Environment Software.... 57
B
Block Diagram On-Chip Reset Circuit ................................................. 37 Timer0......................................................................... 27 TMR0/WDT Prescaler................................................. 30 Watchdog Timer.......................................................... 39 Brown-Out Protection Circuit .............................................. 40
O
OPTION Register ............................................................... 15 OSC selection..................................................................... 31 OSCCAL Register .............................................................. 16 Oscillator Configurations .................................................... 32 Oscillator Types HS............................................................................... 32 LP ............................................................................... 32 RC .............................................................................. 32 XT ............................................................................... 32
C
CAL0 bit .............................................................................. 16 CAL1 bit .............................................................................. 16 CAL2 bit .............................................................................. 16 CAL3 bit .............................................................................. 16 CALFST bit ......................................................................... 16 CALSLW bit ........................................................................ 16 Carry ..................................................................................... 7 Clocking Scheme ................................................................ 10 Code Protection ............................................................ 31, 41 Configuration Bits................................................................ 31 Configuration Word ............................................................. 31
P
Package Marking Information ............................................. 81 Packaging Information ........................................................ 81 PC....................................................................................... 17 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 56 PICDEM-2 Low-Cost PIC16CXX Demo Board................... 56 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 56 PICSTART(R) Plus Entry Level Development System......... 55 POR Device Reset Timer (DRT) ................................... 31, 38 PD............................................................................... 40 Power-On Reset (POR).............................................. 31 TO............................................................................... 40 PORTA ............................................................................... 19 Power-Down Mode ............................................................. 41 Prescaler ............................................................................ 30 PRO MATE(R) II Universal Programmer .............................. 55 Program Counter ................................................................ 17
D
DC and AC Characteristics ................................................. 77 Development Support ......................................................... 55 Development Tools ............................................................. 55 Device Varieties .................................................................... 5 Digit Carry ............................................................................. 7
E
EEPROM Peripheral Operation .......................................... 21 Errata .................................................................................... 2
Q
Q cycles .............................................................................. 10
F
Family of Devices.................................................................. 4 Features................................................................................ 1 FSR..................................................................................... 18 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) .................... 57
R
RC Oscillator ...................................................................... 33 Read Modify Write .............................................................. 20 Register File Map ............................................................... 12 Registers Special Function ......................................................... 13 Reset .................................................................................. 31 Reset on Brown-Out ........................................................... 40
I
I/O Interfacing ..................................................................... 19 I/O Port................................................................................ 19 I/O Programming Considerations........................................ 20 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 55 ID Locations .................................................................. 31, 41 INDF.................................................................................... 18 Indirect Data Addressing..................................................... 18 Instruction Cycle ................................................................. 10 Instruction Flow/Pipelining .................................................. 10 Instruction Set Summary..................................................... 44
S
SEEVAL(R) Evaluation and Programming System .............. 57 SLEEP .......................................................................... 31, 41 Software Simulator (MPLAB-SIM) ...................................... 57 Special Features of the CPU .............................................. 31 Special Function Registers ................................................. 13 Stack................................................................................... 17 STATUS ................................................................................7 STATUS Register ............................................................... 14
K
KeeLoq(R) Evaluation and Programming Tools.................... 58
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 87
PIC12CE5XX
T
Timer0 Switching Prescaler Assignment................................. 30 Timer0......................................................................... 27 Timer0 (TMR0) Module............................................... 27 TMR0 with External Clock........................................... 29 Timing Parameter Symbology and Load Conditions........... 64 TRIS Registers.................................................................... 19
W
Wake-up from SLEEP ......................................................... 41 Watchdog Timer (WDT) ................................................ 31, 38 Period.......................................................................... 39 Programming Considerations ..................................... 39 WWW, On-Line Support........................................................ 2
Z
Zero bit .................................................................................. 7
DS40172B-page 88
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
980106
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
(c) 1998 Microchip Technology Inc.
DS40172B-page 89
PIC12CE5XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC12CE5XX Questions: 1. What are the best features of this document? Y N Literature Number: DS40172B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40172B-page 90
PIC12CE5XX
PIC12CE5XX Product Identification System
PART NO. -XX X /XX XXX Pattern: Package: Special Requirements SN SM P JW I E 04 = = = = = = = = 150 mil SOIC 208 mil SOIC 300 mil PDIP 300 mil Windowed CERDIP 0C to +70C -40C to +85C -40C to +125C 4 MHz Examples
a) PIC12CE518-04/P Commercial Temp., PDIP Package, 4 MHz, normal VDD limits PIC12CE518-04I/SM Industrial Temp., SOIC package, 4 MHz, normal VDD limits PIC12CE519-04I/P Industrial Temp., PDIP package, 4 MHz, normal VDD limits
b)
Temperature Range: Frequency Range: Device
c)
PIC12CE518 PIC12CE519 PIC12CE518T (Tape & reel for SOIC only) PIC12CE519T (Tape & reel for SOIC only) PIC12LCE518 PIC12LCE519 PIC12LCE518T (Tape & reel for SOIC only) PIC12LCE519T (Tape & reel for SOIC only)
Please contact your local sales office for exact ordering procedures.
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 89
PIC12CE5XX
NOTES:
DS40172B-page 90
Preliminary
(c) 1998 Microchip Technology Inc.
PIC12CE5XX
(c) 1998 Microchip Technology Inc.
Preliminary
DS40172B-page 91
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dallas
Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Detroit
Microchip Technology Inc. 42705 Grand River, Suite 201 Novi, MI 48375-1727 Tel: 248-374-1888 Fax: 248-374-2874
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-689 9939 Fax: 39-39-6899883 7/7/98
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicroTM 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).
All rights reserved. (c) 8/31/98, Microchip Technology Incorporated, USA. Monday, August 31, 1998
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40172B-page 92
(c) 1998 Microchip Technology Inc.

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